This invention relates to a method and apparatus for driving a solid state camera, especially a method for driving a solid state camera having high sensitivity.
A solid state camera using a single-chip solid state image sensor has many advantages over a conventional tube type camera, such as small scale, light weight, low power consumption, no sticking, no image lag, long life and stability. On the other hand, the solid state camera has some inherent problems, such as vertical smear, fixed pattern noise (hereinafter FPN) and blooming. Especially, the vertical smear is a serious problem, which is not generated in the conventional tube type camera.
There are three types of the solid state camera in the market, that is, the Metal Oxide Semiconductor type, the Charge Priming Device type and the Charge Coupled Device type (hereinafter MOS type, CPD type and CCD type, respectively). The CPD type solid state camera is able to sweep out vertical smear charges from vertical signal lines to the outside prior to reading out signal charges from photodiodes to the vertical signal lines, so that it can easily suppress the vertical smear.
Hereinafter, examples of this CPD type solid state camera are explained using the FIGS. 1, 2 and 3. FIG. 1 shows an example of the CPD type solid state camera having a circuit for sweeping out the vertical smear charges. The numerals 1, 2 and 3 denote a photodiode, a MOS transistor used as a vertical switch, and a vertical signal line, respectively. The numeral 9 designates a charge transfer device (hereinafter CTD, for example, a buried channel type CCD), which can transfer the signal charges of the photodiodes belonging to two adjacent horizontal rows during a horizonal scanning period. A combination part constructed by MOS transistors 4 to 8 combines the vertical signal line 3 and the CTD 9. The MOS transistor 5 is preferably a depletion type used as a capacitance. The numeral 10 denotes a vertical scanning circuit, each output of which is connected to each vertical gate line 11.
In the first increment of the horizontal blanking period, excess charges, which are generated by vertical smear, blooming, etc. are swept out from the vertical signal lines 3 through the transistors 4, 5, 6 and 7 to a blooming sweep out drain (hereinafter BD). After that, the signal charges of the photodiodes 1 belonging to the designated horizontal line are read into the vertical signal lines 3 and are transferred to the CTD 9 through the transistors 4, 5, 6 and 8. Usually, this execution is repeated twice so that the signal charges of two adjacent horizontal lines are transferred to the CTD9. During the following horizontal period, the CTD9 is scanned to supply the signal charges to an output terminal. The method of simultaneously reading out the video signal of the two adjacent horizontal lines is not directly related to this invention, but it is effective to get a single-chip solid state color camera having high picture quality.
FIGS. 2A and 2B show an equivalent circuit and driving pulses of the CPD type solid state camera shown in FIG. 1, respectively. The equivalent circuit shown in FIG. 2A is related to a signal charge transferring path from one of the photodiodes 1 to the CTD9. Cpd, Cv and C4 indicate capacitances of the photodiode 1, the vertical signal line 3 and the gate of the transistor 5, respectively. T1, T2, T3 and T4 indicate driving pulses for the gates of the MOS transistors 8, 6, 4 and 5, respectively. H1 indicates one of clock pulses for driving the CTD9. Referring to FIG. 2B, time periods t1-t9 construct one horizontal blanking period. During the time period t1, inner bias charges are poured into the capacitance Cv from the capacitance C4, and the excess charges accumulated in the capacitance Cv are efficiently transferred to the capacitance C4 together with the inner bias charges. During the time period t2, outer bias charges are injected into the capacitance C4 from the BD in the form of the constant voltage. Concurrently with the injection, the excess charges are swept out from the capacitance C4 to the BD. After that, the outer bias charges are swept out to the BD. As the transistor 4 is in the OFF state during the time period t2 (see the driving pulse T3 shown in FIG. 2B), the signal charges in the capacitance Cpd can be read out to the capacitance Cv by making the pulse VG corresponding to the designated horizontal line into the ON state. During the time period t3, the inner bias charges are poured again from the capacitance C4 into the capacitance Cv, and the signal charges in the capacitance Cv are efficiently transferred to the capacitance C4 together with the inner bias charges. During the time period t4, other outer bias charges (hereinafter CTD bias charges) are injected from the CTD 9 to the capacitance C4, and the signal charges are efficiently read out from the capacitance C4 into the CTD 9 together with the CTD bias charges. During the time period t5, all the signal charges in the CTD 9 are shifted by one stage. During the time periods t6-t9, the same process as mentioned above is executed except that the adjacent horizontal line is designated. For example, if the pulse VG depicted as a continuous line corresponds to the pulse VGn+2 shown in FIG. 1, the pulse VG drawn by a dotted line corresponds to the pulse VGn+1 shown in FIG. 1.
The reason for using the bias charges in the process of transferring charges from the capacitance Cv to the capacitance C4, and from the capacitance C4 to CTD 9 is to improve a transfer efficiency. Generally, in a case where small signal charges are transferred from a capacitance C through a MOS transistor in a saturated region having a channel conductance .beta. with bias charges B during a transfer period .tau., a transfer inefficiency .epsilon. is shown by the following formula: ##EQU1## Accordingly, using the bias charges is a usual practice in order to improve the transfer efficiency.
Now, the formula (1) shows that the transfer efficiency is sensitive to the capacitance C. The capacitance Cv is several pF and extremely larger than other capacitances (Cpd.apprxeq.0.05 pF, C4.apprxeq.0.1 pF). Therefore, in order to efficiently transfer the charges from the capacitance Cv, it is necessary to enlarge the bias charges B because it is difficult, as a practical matter, to enlarge the transfer period .tau. and the channel conductance .beta.. So, the conventional method using the inner bias charges is very useful. In this method, to enlarge the bias charges B infinitely does not result in reduction of the dynamic range, because the inner bias charges come and go only between the capacitance Cv and the capacitance C4. Further, if the driving pulses T2, T3 and T4 balance between the sweep out period and the read out period, the FPN does not generate in the charge transferring process from the capacitance Cv to the capacitance C4.
Next, the suppression effect of the vertical smear will be explained. There are two types of the vertical smear, which are not swept out and are read out. One type of the vertical smear is due to bad transfer efficiency in the sweep out period. Another type of the vertical smear is generated by the mixture of the charges in the vertical signal line 3 during the period from the end of sweeping out the excess charges from the capacitance Cv to the end of reading out the signal charges from the capacitance Cv. If the radio of the period (t2+t3+t7+t8), which corresponds to a non-sweep out period, to the horizontal period (about 64 .mu.S) is .alpha., and the transfer inefficiency .epsilon. from the capacitance Cv to the capacitance C4 is .epsilon.v, a reducing rate R of the vertical smear by means of the sweep out is shown as the following formula: EQU R=.epsilon.v(1-.alpha.)+.alpha. (2)
It is apparent from the formula (2) that the vertical smear can be endlessly suppressed by raising up the transfer efficiency and shortening the transfer period .tau.. However, as the formula (1) shows, raising up the transfer efficiency conflicts with shortening the transfer period .tau.. So, in the CPD type solid state camera shown in FIG. 1, a desirable reducing rate R of about 0.1 (-20 dB) is not feasible.
FIG. 3 shows another example of the CPD type solid state camera which is improved at this point. The difference between the example shown in FIG. 3 and the one shown in FIG. 1 is that the former circuit has an inverter 22 constructed by an enhancement type MOS transistor 20 and a depletion type MOS transistor 21, an input of which is connected to the vertical signal line 3 and an output of which is connected to the gate of the MOS transistor 4. The timing of the driving pulses is the same as the one shown in FIG. 2B except that the driving pulse T3 is supplied to a terminal VD, and a terminal VS is connected to the ground. The effect of adding the inverter 22 having a gain (-G) is to equivalently make the capacitance of the vertical signal line 3 Cv/(1+G). Apparently from the formula (1), the inverter 22 immensely contributes to the improvement of the transfer efficiency so that the reducing rate R shown in the formula (2) can readily be made lower than 0.1 (-20 dB).
Now, as mentioned above, the CPD type solid state camera can be expected to be superior in picture quality and sensitivity to the MOS type solid state camera. On the other hand, the CCD type solid state camera has some problems, i.e., image lag, vertical smear and a roughness of a color filter arrangement in the vertical direction so that it is inferior in picture quality to the CPD type and the MOS type. However, it is superior in sensitivity when compared to the other types. In the CCD type, the factor of reducing sensitivity is random noise generated in a horizonal transferring CCD, which corresponds to the CTD9 shown in FIGS. 1 and 3. On the other hand, in the CPD type, there are other factors of suppressing sensitivity, i.e., random noise, FPN and shading generated in the combination part (i.e., the transistors 4 to 8 which combine the vertical signal line 3 to the CTD9). However, in the CPD type, an aperture ratio of the photodiode is about two times as large as one of the CCD type so that the CPD type is superior in all aspects to the CCD type, if total noise of the CPD type is reduced lower than half of one of the CCD type.
So, hereinafter, the random noise, the FPN and the shading generated in the combination part will be explained. The random noise is mainly generated in the charge transfer process from the capacitance Cv to the capacitance C4. FIG. 4 illustrates randon charge fluctuations q1,q2,--on the capacitance Cv in the same time scale as one shown in FIG. 2B. When the transistor 4 is in the OFF state, that is, the time periods t2, t4, t5, t7 and t9, the charges on the capacitance Cv do not vary. Further, if the transfer efficiency from the capacitance Cv to the capacitance C4 is sufficiently high, the charge fluctuations q1, q2--have no correlation, mutually. The main cause of the charge fluctuations q1,q2,--of the camera shown in FIG. 3 differs from one of the camera shown in FIG. 1. In the latter, they come from thermal noise generated in the channel of the MOS transistor 4, and in the former, they are caused by random noise generated in the inverter 22 and the variation of the gate voltage of the MOS transistor 4 with random noise. In both of them, the charge fluctuations can be illustrated by FIG. 4. During the time period t3, noise charges (q3-q2) are read out and during the time period t8, noise charges (q5-q4) are read out. Assuming that a root means square value (hereinafter rms value) of the charge fluctuations q1,q2--is qn, the rms value of random noise charges per one picture element becomes .sqroot.2 qn. The random noise generated in the charge transfer process from the capacitance C4 to the CTD9 or the BD can be neglected, because the capacitance C4 is extremely smaller than the capacitance Cv.
On the contrary, the FPN is generated in the charge transfer process from the capacitance C4 to the CTD 9 or the BD. There are two kinds of the FPN in the charge transfer process from the capacitance C4, one of which comes from a dispersion .DELTA.B of the bias charges. The CTD bias charges, which are injected into the CTD 9, for example, by the potential balance method, do not have the dispersion theoretically, but in fact have the dispersion caused by the dispersion in shapes of the transfer gates of the CTD 9. If all the CTD bias charges can be injected into the combination part, the injection dispersion does not occur. However, the charges do not flow easily in the direction to the combination part. So, as all the CTD bias charges can not be injected to the combination part, the injection dispersion .DELTA.B exist. As a result, the FPN comes from a leftover part of the injection dispersion .DELTA.B. With the same manner described above, the injection dispersion of the outer bias charges generates the FPN.
Another kind of the FPN is caused by a structure of the gate of the MOS transistor 6. FIG. 5 illustrates a plane figure of the gates of the MOS transistors 5 to 8. Apparently from FIG. 5, the gate of MOS transistor 6 has a narrow part, which can control a current flow by itself. However, there is a difference of the current flows between the side of the CTD 9 and the side of the BD, so that effective threshold voltages are different. The difference .DELTA.Vt of the threshold voltages disperses in response to the dispersion of the parameters of the MOS transistor 6. If this dispersion is .DELTA..DELTA.Vt and the dispersion of the capacitance C4 is .DELTA.C4, the charges (.DELTA.C4..DELTA.Vt+C4..DELTA..DELTA.Vt) of the FPN generate per one picture element.
The shading comes from a long time constant of the vertical gate line 11. As the vertical gate line 11 is made of poli-silicon, it has the time constant, approximately equal to 1 us. Therefore, even if the pulse VG has an ideal wave form shown in FIG. 2B at the left end of the vertical gate line 11, the pulse VG becomes to have a dull wave form at the right end thereof. So, the response does not completely cease at the next read out period t3. The vertical gate line 11 crosses over the vertical signal line 3 and there is a large capacitive coupling so that the shading in the horizontal direction generates.